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features and benefits ? low r ds(on) outputs ? internal mixed current decay mode ? synchronous rectification for low power dissipation ? internal uvlo ? crossover-current protection ? 3.3 and 5 v compatible logic supply ? thin profile qfn and tssop packages ? thermal shutdown circuitry ? short-to-ground protection ? shorted load protection ? low current sleep mode, < 10 a description the a4987 is a dual dmos full-bridge stepper motor driver with parallel input communication and overcurrent protection. each full-bridge output is rated up to 35 v and 1 a. the a4987 includes fixed off-time pulse width modulation (pwm) current regulators, along with 2- bit nonlinear dacs (digital-to-analog converters) that allow stepper motors to be controlled in full, half, and quarter steps. the pwm current regulator uses the allegro ? patented mixed decay mode for reduced audible motor noise, increased step accuracy, and reduced power dissipation. internal synchronous rectification control circuitry is provided to improve power dissipation during pwm operation. the outputs are protected from shorted load and short-to- ground events, which protect the driver and associated circuitry from thermal damage or flare-ups. other protection features include thermal shutdown with hysteresis, undervoltage lockout (uvlo) and crossover current protection. special power-up sequencing is not required. the a4987 is supplied in two packages, a 24-contact qfn (es) and a 24-pin tssop (lp). both packages have exposed thermal pads for enhanced thermal performance. the 24-contact es is 4 mm 4 mm, with a nominal overall package height of 0.75 mm. the 24-pin lp is a tssop with 0.65 pitch and an overall package height of 1.2 mm. both packages are lead (pb) free, with 100% matte tin leadframe plating. 4987-ds, rev. 5 dmos dual full-bridge pwm motor driver with overcurrent protection a4987 typical application diagram microcontroller or controller logic v dd vref gnd gnd ph2 in12 sleep in11 ph1 in02 in01 vbb1 cp1 vcp vreg vdd rosc 0.22 f 0.22 f 0.1 f0.1 f 100 f cp2 vbb2 out1a out1b sense1 out2a out2b sense2 a4987 24-contact qfn 4 mm 4 mm 0.75 mm (es package) packages : 24-pin tssop with exposed thermal pad (lp package) approximate size
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 35 v output current i out 1 a logic input voltage v in ?0.3 to 5.5 v logic supply voltage v dd ?0.3 to 5.5 v motor outputs voltage ?2.0 to 37 v sense voltage v sense ?0.5 to 0.5 v reference voltage v ref 5.5 v operating ambient temperature t a range s ?20 to 85 oc maximum junction t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number package packing A4987SESTR-T 24-pin qfn with exposed thermal pad 1500 pieces per 7-in. reel a4987slptr-t 24-pin tssop with exposed thermal pad 4000 pieces per 13-in. reel
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional block diagram 0.1 f regulator gate drive charge pump dmos full-bridge 1 0.1 f dmos full-bridge 2 v cp pwm latch blanking mixed decay to v bb2 in02 ph1 in11 sense1 out1b out1a vbb1 sense2 out2b out2a vbb2 vcp cp2 cp1 vreg vdd control logic osc osc v reg 0.22 f sense2 in01 in12 ph2 dac +- v ref sense2 rosc gnd gnd sleep ocp ocp dac + - v ref pwm latch blanking mixed decay osc sense2 v reg ref v ref
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics 1 at t a = 25c, v bb = 35 v (unless otherwise noted) characteristics symbol test conditions min. typ. 2 max. units output drivers load supply voltage range v bb operating 8 ? 35 v during sleep mode 0 ? 35 v logic supply voltage range v dd operating 3.0 ? 5.5 v output on resistance r ds(on) source driver, i out = ?800 ma ? 700 900 m sink driver, i out = 800 ma ? 700 900 m body diode forward voltage v f source diode, i f = ?800 ma ? ? 1.3 v sink diode, i f = 800 ma ? ? 1.3 v motor supply current i bb f pwm < 50 khz ? ? 4 ma operating, outputs disabled ? ? 2 ma sleep mode ? ? 10 a logic supply current i dd f pwm < 50 khz ? ? 8 ma outputs off ? ? 5 ma sleep mode ? ? 10 a control logic logic input voltage v in(1) v dd ? 0.7 ??v v in(0) ?? v dd ? 0.3 v logic input current i in(1) v in = v dd ? 0.7 ?20 <1.0 20 a i in(0) v in = v dd ? 0.3 ?20 <1.0 20 a logic input pull-down r in02 ? 100 ? k r in12 ?50?k logic input hysteresis v hys(in) as a % of v dd 51119% blank time t blank 0.7 1 1.3 s fixed off-time t off osc = vdd or gnd 20 30 40 s r osc = 25 k 23 30 37 s reference input voltage range v ref 0?4v reference input current i ref ?3 0 3 a current trip-level error 3 err i v ref = 2 v, %i tripmax = 33.3% ? ? 15 % v ref = 2 v, %i tripmax = 66.7% ? ? 5 % v ref = 2 v, %i tripmax = 100.00% ? ? 5 % crossover dead time t dt 100 475 800 ns protection overcurrent protection threshold 4 i ocpst 1.1 ? ? a thermal shutdown temperature t tsd ? 165 ? c thermal shutdown hysteresis t tsdhys ?15?c vdd undervoltage lockout v dduvlo v dd rising 2.7 2.8 2.9 v vdd undervoltage hysteresis v dduvlohys ?90?mv 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. 3 v err = [(v ref /8) ? v sense ] / (v ref /8). 4 overcurrent protection (ocp) is tested at t a = 25c in a restricted range and guaranteed by characterization.
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com thermal characteristics may require derating at maximum conditions characteristic symbol test conditions* value units package thermal resistance r ja es package; estimated, on 4-layer pcb, based on jedec standard 37 oc/w lp package; on 4-layer pcb, based on jedec standard 28 oc/w *in still air. additional thermal information available on allegro web site. 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (w) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 maximum power dissipation, p d (max) (r ja = 37 oc/w) (r ja = 28 oc/w)
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional description device operation. the a4987 is designed to operate one stepper motor in full, half, or quarter step mode. the currents in each of the output full-bridges, all n-channel dmos, are regu- lated with fixed off-time pulse width modulated (pwm) control circuitry. each full-bridge peak current is set by the value of an external current sense resistor, r s x , and a reference voltage, v ref x . percentages of the peak current are set using a 2-bit nonlinear dac that programs 33%, 66%, or 100% of the peak current, or disables the outputs. internal pwm current control. each full-bridge is con- trolled by a fixed off-time pwm current control circuit that limits the load current to a desired value, i trip . initially, a diagonal pair of source and sink fet outputs are enabled and current flows through the motor winding and the current sense resistor, r s x . when the voltage across r s x equals the dac output voltage, the current sense comparator resets the pwm latch. the latch then turns off the appropriate source driver and initiates a fixed off time decay mode. the maximum value of current limiting is set by the selection of r s x and the voltage at the vref pin. the transconductance func- tion is approximated by the maximum value of current limiting, i tripmax (a), which is set by i tripmax = v ref / ( 8 ? r s ) where r s is the resistance of the sense resistor ( ) and v ref is the input voltage on the ref pin (v). the 2-bit dac output reduces the v ref output to the current sense comparator in precise steps, such that i trip = (%i tripmax / 100) i tripmax it is critical that the maximum rating (0.5 v) on the sense1 and sense2 pins is not exceeded. fixed off-time. the internal pwm current control circuitry uses a one-shot circuit to control the duration of time that the dmos fets remain off. the off-time, t off , is determined by the rosc terminal. the rosc terminal has two settings: ? rosc tied to vdd or ground ? off-time internally set to 30 s ? rosc through a resistor to ground ? off-time is determined by the following formula: t off r osc 825 blanking. this function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. the comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. the blank time, t blank ( s), is approximately t blank 1 s shorted-load and short-to-ground protection. if the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protect- ing the device from damage. in the case of a short-to-ground, the device will remain disabled (latched) until the s l e e p input goes high or vdd power is removed. a short-to-ground overcurrent event is shown in figure 1. when the two outputs are shorted together, the current path is through the sense resistor. after the blanking time ( 1 s) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. this causes the driver to go into a fixed off-time cycle. after the fixed off-time expires the driver turns on again and the process repeats. in this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. this condition is shown in figure 2. during a shorted load event it is normal to observe both a posi- tive and negative current spike as shown in figure 3, due to the direction change implemented by the mixed decay feature. this is shown in figure 3. in both instances the overcurrent circuitry is protecting the driver and prevents damage to the device. functional description
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com charge pump (cp1 and cp2). the charge pump is used to generate a gate supply greater than that of vbb for driving the source-side fet gates. a 0.1 f ceramic capacitor, should be connected between cp1 and cp2. in addition, a 0.1 f ceramic capacitor is required between vcp and vbb, to act as a reservoir for operating the high-side fet gates. capacitor values should be class 2 dielectric 15% maximum, or tolerance r, according to eia (electronic industries alliance) specifications. v reg (vreg) . this internally-generated voltage is used to operate the sink-side fet outputs. the nominal output voltage of the vreg terminal is 7 v. the vreg pin must be decoupled with a 0.22 f ceramic capacitor to ground. v reg is internally monitored. in the case of a fault condition, the fet outputs of the a4987 are disabled. capacitor values should be class 2 dielectric 15% maximum, or tolerance r, according to eia (electronic industries alliance) specifications. shutdown. in the event of a fault, overtemperature (excess t j ) or an undervoltage (on vcp), the fet outputs of the a4987 are disabled until the fault condition is removed. at power-on, the uvlo (undervoltage lockout) circuit disables the fet outputs and resets the translator to the home state. sleep mode ( s l e e p ). to minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output fets, current regulator, and charge pump. a logic low on the s l e e p pin puts the a4987 into sleep mode. when emerging from sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issu- ing a logic command. mixed decay operation. the bridge operates in mixed decay mode, as shown in figures 5 through 7. as the trip point is reached, the a4987 initially goes into a fast decay mode for 31.25% of the off-time, t off . after that, it switches to slow decay mode for the remainder of t off . a timing diagram for this feature appears in figure 4. synchronous rectification . when a pwm-off cycle is triggered by an internal fixed-off time cycle, load current recir- culates in mixed decay mode. this synchronous rectification feature turns on the appropriate fets during current decay, and effectively shorts out the body diodes with the low fet r ds(on) . this reduces power dissipation significantly, and can eliminate the need for external schottky diodes in many applications. syn- chronous rectification turns off when the load current approaches zero (0 a), preventing reversal of the load current. t fixed off-time 5 a / div. t 5 a / div. figure 2. shorted load (outxa outxb) in slow decay mode figure 3. shorted load (outxa outxb) in mixed decay mode fixed off-time fast decay portion (direction change) t fault latched 5 a / div. figure 1. short-to-ground event
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com symbol characteristic t off device fixed off-time i peak maximum output current t sd slow decay interval t fd fast decay interval i out device output current figure 4. current decay modes timing chart i out i out t see enlargement a enlargement a t sd t fd t off slow decay mixed decay fast decay i peak 70.71 C70.71 0 100.00 C100.00 phx inx1 inx2
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com application layout layout . the printed circuit board should use a heavy ground- plane. for optimum electrical and thermal performance, the a4987 must be soldered directly onto the board. on the under- side of the a4987 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. in order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground , located very close to the device. by making the connection between the pad and the ground plane directly under the a4987, that area becomes an ideal location for a star ground point. a low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. the two input capacitors should be placed in parallel, and as close to the device supply pins as possible. the ceramic capaci- tor (cin1) should be closer to the pins than the bulk capacitor (cin2). this is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. the sense resistors, r sx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. the sensex pins have very short traces to the r sx resistors and very thick, low impedance traces directly to the star ground underneath the device. if possible, there should be no other components on the sense circuits. pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) solder a4987 v dd v bb c2 rosc pad a4987 c6 c7 c3 c4 r4 r5 c1 out2b out1a out1b out2a vbb2 sense2 out2a out1a sense1 vbb1 out2b ph2 gnd cp1 cp2 vcp out1b ph1 gnd ref in01 vdd vreg in02 in12 in11 rosc sleep r4 u1 out2b gnd r5 out2a out1a out1b gnd gnd gnd c3 c4 c6 rosc c2 c7 c1 vbb vdd capacitance bulk es package configuration shown
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com v dd v bb c2 rosc pad a4987 c5 c6 c3 c4 r4 r5 c1 out2b out1b out2a out1a vbb2 vbb1 ph1 sense2 sense1 cp1 gnd ph2 gnd cp2 vcp vreg rosc vdd ino2 in12 in11 in01 ref sleep gnd gnd gnd gnd gnd gnd gnd r4 u1 out2b gnd r5 out2a out1a out1b c3 c4 c5 rosc c2 c6 c1 vbb vdd capacitance bulk lp package typical application and circuit layout
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com vcp gnd cp2 gnd cp1 v bb 8 v gnd vdd gnd gnd 8 v gnd gnd 8 v v bb vreg 10 v gnd dmos parasitic sense v reg gnd vbb 40 v gnd v bb out dmos parasitic dmos parasitic gnd pgnd gnd in01 in02 in11 in12 ph1 ph2 vref rosc sleep pin circuit diagrams
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 12 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 5. step sequencing for full-step increments. 0 100.0 66.7 ?100.0 ?66.7 (%) phase 1 0 100.0 66.7 ?100.0 ?66.7 (%) phase 2 full step 2 phase modified full step 2 phase step sequencing diagrams 0 100.0 66.7 ?100.0 ?66.7 (%) phase 1 0 100.0 66.7 ?100.0 ?66.7 (%) phase 2 half step 2 phase modified half step 2 phase figure 6. step sequencing for half-step increments.
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 13 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 0 100.0 66.7 33.3 ?33.3 ?100.0 ?66.7 0 100.0 66.7 33.3 ?33.3 ?100.0 ?66.7 (%) phase 1 (%) phase 2 figure 7. step sequence for quarter-step increments step sequencing settings full 1/2 1/4 phase 1 (%i tripmax ) i01 i11 phase phase 2 (%i tripmax ) i02 i12 phase 11 0 hhx 100ll1 2 33 l h 1 100 l l 1 1 2 3 100/66* l/h* l 1 100/66* l/h* l 1 4 100 l l 1 33 l h 1 3 5 100 l l 1 0 h h x 6 100 l l 1 33 l h 0 2 4 7 100/66* l/h* l 1 100/66* l/h* l 0 8 33 l h 1 100 l l 0 59 0 hhx 100ll0 10 33 l h 0 100 l l 0 3 6 11 100/66* l/h* l 0 100/66* l/h* l 0 12 100 l l 0 33 l h 0 7 13 100 l l 0 0 h h x 14 100 l l 0 33 l h 1 4 8 15 100/66* l/h* l 0 100/66* l/h* l 1 16 33 l h 0 100 l l 1 * denotes modified step mode
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 14 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com terminal list table name number description es lp cp1 4 1 charge pump capacitor terminal cp2 5 2 charge pump capacitor terminal ph1 17 14 logic input ph2 2 23 logic input gnd 3, 16 13, 24 ground* in02 8 5 logic input in12 9 6 logic input nc ? ? no connection out1a 21 18 dmos full bridge 1 output a out1b 18 15 dmos full bridge 1 output b out2a 22 19 dmos full bridge 2 output a out2b 1 22 dmos full bridge 2 output b ref 15 12 g m reference voltage input in11 10 7 logic input rosc 11 8 timing set sense1 20 17 sense resistor terminal for bridge 1 sense2 23 20 sense resistor terminal for bridge 2 s l e e p 12 9 logic input in01 14 11 logic input vbb1 19 16 load supply vbb2 24 21 load supply vcp 6 3 reservoir capacitor terminal vdd 13 10 logic supply vreg 7 4 regulator decoupling terminal pad ? ? exposed pad for enhanced thermal dissipation* *the gnd pins must be tied together externally by connecting to the pad ground plane under the device. pad 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 vbb2 sense2 out2a out1a sense1 vbb1 vreg in02 in12 in11 rosc sleep out1b ph1 gnd ref in01 vdd out2b ph2 gnd cp1 cp2 vcp pin-out diagrams es package lp package 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd ph2 out2b vbb2 sense2 out2a out1a sense1 vbb1 out1b ph1 gnd cp1 cp2 vcp vreg in02 in12 in11 rosc sleep vdd in01 ref pad
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 15 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com es package, 24-pin qfn with exposed thermal pad 0.95 c seating plane c 0.08 25x 24 24 2 1 1 2 24 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only; not for tooling use (reference jedec mo-220wggd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-25w6m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.30 0.50 4.10 0.50 bsc 4.00 0.15 4.00 0.15 2.70 2.70 2.70 2.70 0.75 0.05 0.45 max b pcb layout reference view 0.25 +0.05 ?0.07
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 16 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com lp package, 24-pin tssop with exposed thermal pad 1.20 max c seating plane 0.15 max c 0.10 24x 0.65 6.10 3.00 4.32 1.65 0.45 0.65 0.25 2 1 24 3.000.05 4.320.05 (1.00) gauge plane seating plane b a a terminal #1 mark area b for reference only (reference jedec mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c 7.80 0.10 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06
dmos dual full-bridge pwm motor driver with overcurrent protection a4987 17 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com copyright ?2009-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 5 march 21, 2012 update step sequence and example layout

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